Core Infinity listening impressions and comparisons

[Jean-Marie]

Yes, I got confirmation that all sources get their clock (improved) from the CI board, therefore improvement in applicable for every entry, not only to the Air/Streaming.

Jean-Marie

This would appear to be consistent with the information @Celts88 posted a while back.  To be honest, I am not sure if this is good news.  Consider that the reason devices like the Mutec MC3+USB and Mutec REF10 can deliver such good results is because the AES/EBU input is a synchronous input, so it derives it's clock from the source feed.  However, if the AES/EBU input is now deriving it's clock from the CI board then it is effectively configured as an asynchronous input, thus removing the potential for 'super clock' devices like the Mutec REF10 to deliver the clock signal.

Yes, I got confirmation that all sources get their clock (improved) from the CI board, therefore improvement in applicable for every entry, not only to the Air/Streaming.

Jean-Marie

This would appear to be consistent with the information @Celts88 posted a while back.  To be honest, I am not sure if this is good news.  Consider that the reason devices like the Mutec MC3+USB and Mutec REF10 can deliver such good results is because the AES/EBU input is a synchronous input, so it derives it's clock from the source feed.  However, if the AES/EBU input is now deriving it's clock from the CI board then it is effectively configured as an asynchronous input, thus removing the potential for 'super clock' devices like the Mutec REF10 to deliver the clock signal.

Strange though, how could that work?
Surely the SPDIF and AES/EBU input have to be clocked by the source to maintain long term synchronisation. Trying to use 2 slightly different clocks was a source of early AIR dropout problems iirc.
Since there is no mechanism to send timing data back from the Devialet clock to the supplying source in the AES/EBU standard (or any way for the source to synchronise thus anyway) I think there much have been some misunderstanding somewhere.

I’m not a hardware designer, so I did not enter in any details. I would assume that for synchronous entries they may be driving the internal clock of the Devialet, which would be equally true for the new clock on the CI. If the clock on the CI is better than the previous one it is not too far fetch to think that the locking from synchronous sources has been improved too. 

Jean-Marie