@Confused From what I've picked up, from (e.g.) John Swenson's posts, the point of reducing clock phase noise is mainly to do with its effects on the PHY devices, which might (it is supposed) inject analog noise into the DAC (e.g. via power/ground planes). As you say, it should not have any effect on the timing of samples reaching the DAC because they are clocked out of a ton of buffer memory by a clock that is completely asychronous to the Ethernet.
Roon (Mac Mini), Wilson Benesch Full Circle, Expert 1000 Pro CI, Kaiser Chiara
Warwickshire, UK
